Interposer systems for information handling systems

ABSTRACT

A computing apparatus including a printed circuit board (PCB) including a first central processing unit (CPU) socket and additional CPU socket(s); a CPU coupled to the first CPU socket; a base interposer coupled to the additional CPU socket(s); and one or more devices connected to the base interposer, wherein the base interposer provides a connection between the CPU and the one or more devices.

BACKGROUND Field of the Disclosure

The disclosure relates generally to information handling systems, and,more particularly, to interposer systems for information handlingsystems.

Description of the Related Art

As the value and use of information continues to increase, individualsand businesses seek additional ways to process and store information.One option available to users is information handling systems. Aninformation handling system generally processes, compiles, stores,and/or communicates information or data for business, personal, or otherpurposes thereby allowing users to take advantage of the value of theinformation. Because technology and information handling needs andrequirements vary between different users or applications, informationhandling systems may also vary regarding what information is handled,how the information is handled, how much information is processed,stored, or communicated, and how quickly and efficiently the informationmay be processed, stored, or communicated. The variations in informationhandling systems allow for information handling systems to be general orconfigured for a specific user or specific use such as financialtransaction processing, airline reservations, enterprise data storage,or global communications. In addition, information handling systems mayinclude a variety of hardware and software components that may beconfigured to process, store, and communicate information and mayinclude one or more computer systems, data storage systems, andnetworking systems.

SUMMARY

Innovative aspects of the subject matter described in this specificationmay be embodied in a computing apparatus that includes a printed circuitboard (PCB) including two or more central processing unit (CPU) sockets;a CPU coupled to the primary CPU socket; a base interposer coupled toone or more of the secondary CPU socket(s); and one or more devicesconnected to the base interposer, wherein the base interposer provides aconnection between the CPU and the one or more devices.

These and other embodiments may each optionally include one or more ofthe following features. For instance, the one or more devices includeinput/output devices and the base interposer provides the connectionbetween the CPU and the input/output devices. The connection between theCPU and the input/output devices includes a connection between the CPUand input/output signal traces of the base interposer. The one or moredevices include memory modules and the base interposer provides theconnection between the CPU and the memory modules. The connectionbetween the CPU and the memory modules includes a connection between theCPU and memory signal traces of the base interposer. The apparatusfurther includes a top interposer coupled to the base interposer,wherein the base interposer provides a connection between the CPU andthe top interposer, and the top interposer provides a connection betweenthe base interposer and the one or more devices. The one or more devicesinclude input/output cable connectors and the top interposer providesthe connection between the CPU and the input/output cable connectors.The one or more devices include storage devices, and the top interposerprovides the connection between the CPU and the storage devices. The oneor more devices include a field-programmable gate array (FPGA) devices,and the top interposer provides the connection between the CPU and theFPGA devices The one or more devices includes a peripheral componentinterconnect express (PCIe) devices, and the top interposer provides theconnection between the CPU and the PCIe devices. The top interposerfurther optionally includes a signal integrity boost device.

Innovative aspects of the subject matter described in this specificationmay be embodied in a computing apparatus that includes a printed circuitboard (PCB) including a first central processing unit (CPU) socket and asecond CPU socket; a CPU coupled to the first CPU socket; and aninterposer stack including: a base interposer coupled to the second CPUsocket, a top interposer coupled to the base interposer, wherein aretention mechanism physically couples the top interposer to the PCB.

These and other embodiments may each optionally include one or more ofthe following features. For instance, the retention mechanism includes abracket coupled to the top interposer, the bracket physically couplingthe top interposer to the PCB. The computing apparatus further includesa plurality of memory sockets, wherein the bracket physically couplesthe top interposer to the memory sockets. The computing apparatusfurther includes a plurality of heat sink mounting pins, wherein the topinterposer is physically coupled to the heat sink mounting pins. Theheat sink mounting pins align the top interposer with the baseinterposer. The computing apparatus further includes one or more devicesconnected to the top interposer, wherein the top interposer provides aconnection between the CPU and the one or more devices.

The details of one or more embodiments of the subject matter describedin this specification are set forth in the accompanying drawings and thedescription below. Other potential features, aspects, and advantages ofthe subject matter will become apparent from the description, thedrawings, and the claims.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram of selected elements of an embodiment of aninformation handling system.

FIGS. 2A-2B, 3A-3B, 4A-4B, 5-6, and 7A-7B illustrate respectivecomputing environments for interposers.

FIGS. 8, 9 illustrate a mechanical coupling between the interposer and aprinted circuit board.

DESCRIPTION OF PARTICULAR EMBODIMENT(S)

This document describes an interposer that is coupled to a CPU socket ofa multiprocessor computing system design that allows the lanes of thesecondary CPU socket(s) to be accessed. Specifically, a computingapparatus includes a printed circuit board (PCB) including a primarycentral processing unit (CPU) socket and one or more secondary CPUsocket(s), a CPU coupled to the primary CPU socket, a base interposercoupled to a secondary CPU socket, and one or more devices ultimatelyconnected to the base interposer. The base interposer can provide aconnection between the primary CPU and the one or more devices. In someexamples, the apparatus includes an interposer stack that includes thebase interposer and a top interposer coupled to the base interposer. Thetop interposer provides the connection between the CPU and the devices.

In the following description, details are set forth by way of example tofacilitate discussion of the disclosed subject matter. It should beapparent to a person of ordinary skill in the field, however, that thedisclosed embodiments are exemplary and not exhaustive of all possibleembodiments.

For the purposes of this disclosure, an information handling system mayinclude an instrumentality or aggregate of instrumentalities operable tocompute, classify, process, transmit, receive, retrieve, originate,switch, store, display, manifest, detect, record, reproduce, handle, orutilize various forms of information, intelligence, or data forbusiness, scientific, control, entertainment, or other purposes. Forexample, an information handling system may be a personal computer, aPDA, a consumer electronic device, a network storage device, or anothersuitable device and may vary in size, shape, performance, functionality,and price. The information handling system may include memory, one ormore processing resources such as a central processing unit (CPU) orhardware or software control logic. Additional components of theinformation handling system may include one or more storage devices, oneor more communications ports for communicating with external devices aswell as various input and output (I/O) devices, such as a keyboard, amouse, and a video display. The information handling system may alsoinclude one or more buses operable to transmit communication between thevarious hardware components.

For the purposes of this disclosure, computer-readable media may includean instrumentality or aggregation of instrumentalities that may retaindata and/or instructions for a period of time. Computer-readable mediamay include, without limitation, storage media such as a direct accessstorage device (e.g., a hard disk drive or floppy disk), a sequentialaccess storage device (e.g., a tape disk drive), compact disk, CD-ROM,DVD, random access memory (RAM), read-only memory (ROM), electricallyerasable programmable read-only memory (EEPROM), and/or flash memory(SSD); as well as communications media such wires, optical fibers,microwaves, radio waves, and other electromagnetic and/or opticalcarriers; and/or any combination of the foregoing.

Particular embodiments are best understood by reference to FIGS. 1-6wherein like numbers are used to indicate like and corresponding parts.

Turning now to the drawings, FIG. 1 illustrates a block diagramdepicting selected elements of an information handling system 100 inaccordance with some embodiments of the present disclosure. In variousembodiments, information handling system 100 may represent differenttypes of portable information handling systems, such as, displaydevices, head mounted displays, head mount display systems, smartphones, tablet computers, notebook computers, media players, digitalcameras, 2-in-1 tablet-laptop combination computers, and wirelessorganizers, or other types of portable information handling systems. Inone or more embodiments, information handling system 100 may alsorepresent other types of information handling systems, including desktopcomputers, server systems, controllers, and microcontroller units, amongother types of information handling systems. Components of informationhandling system 100 may include, but are not limited to, a processorsubsystem 120, which may comprise one or more processors, and system bus121 that communicatively couples various system components to processorsubsystem 120 including, for example, a memory subsystem 130, an I/Osubsystem 140, a local storage resource 150, and a network interface160. System bus 121 may represent a variety of suitable types of busstructures, e.g., a memory bus, a peripheral bus, or a local bus usingvarious bus architectures in selected embodiments. For example, sucharchitectures may include, but are not limited to, Micro ChannelArchitecture (MCA) bus, Industry Standard Architecture (ISA) bus,Enhanced ISA (EISA) bus, Peripheral Component Interconnect (PCI) bus,PCI-Express bus, HyperTransport (HT) bus, and Video ElectronicsStandards Association (VESA) local bus.

As depicted in FIG. 1, processor subsystem 120 may comprise a system,device, or apparatus operable to interpret and/or execute programinstructions and/or process data, and may include a microprocessor,microcontroller, digital signal processor (DSP), application specificintegrated circuit (ASIC), or another digital or analog circuitryconfigured to interpret and/or execute program instructions and/orprocess data. In some embodiments, processor subsystem 120 may interpretand/or execute program instructions and/or process data stored locally(e.g., in memory subsystem 130 and/or another component of informationhandling system). In the same or alternative embodiments, processorsubsystem 120 may interpret and/or execute program instructions and/orprocess data stored remotely (e.g., in network storage resource 170).

Also in FIG. 1, memory subsystem 130 may comprise a system, device, orapparatus operable to retain and/or retrieve program instructions and/ordata for a period of time (e.g., computer-readable media). Memorysubsystem 130 may comprise random access memory (RAM), electricallyerasable programmable read-only memory (EEPROM), a PCMCIA card, flashmemory, magnetic storage, opto-magnetic storage, and/or a suitableselection and/or array of volatile or non-volatile memory that retainsdata after power to its associated information handling system, such assystem 100, is powered down.

In information handling system 100, I/O subsystem 140 may comprise asystem, device, or apparatus generally operable to receive and/ortransmit data to/from/within information handling system 100. I/Osubsystem 140 may represent, for example, a variety of communicationinterfaces, graphics interfaces, video interfaces, user inputinterfaces, and/or peripheral interfaces. In various embodiments, I/Osubsystem 140 may be used to support various peripheral devices, such asa touch panel, a display adapter, a keyboard, an accelerometer, a touchpad, a gyroscope, an IR sensor, a microphone, a sensor, or a camera, oranother type of peripheral device.

Local storage resource 150 may comprise computer-readable media (e.g.,hard disk drive, floppy disk drive, CD-ROM, and/or other type ofrotating storage media, flash memory, EEPROM, and/or another type ofsolid state storage media) and may be generally operable to storeinstructions and/or data. Likewise, the network storage resource maycomprise computer-readable media (e.g., hard disk drive, floppy diskdrive, CD-ROM, and/or other type of rotating storage media, flashmemory, EEPROM, and/or other type of solid state storage media) and maybe generally operable to store instructions and/or data.

In FIG. 1, network interface 160 may be a suitable system, apparatus, ordevice operable to serve as an interface between information handlingsystem 100 and a network 110. Network interface 160 may enableinformation handling system 100 to communicate over network 110 using asuitable transmission protocol and/or standard, including, but notlimited to, transmission protocols and/or standards enumerated belowwith respect to the discussion of network 110. In some embodiments,network interface 160 may be communicatively coupled via network 110 toa network storage resource 170. Network 110 may be a public network or aprivate (e.g. corporate) network. The network may be implemented as, ormay be a part of, a storage area network (SAN), personal area network(PAN), local area network (LAN), a metropolitan area network (MAN), awide area network (WAN), a wireless local area network (WLAN), a virtualprivate network (VPN), an intranet, the Internet or another appropriatearchitecture or system that facilitates the communication of signals,data and/or messages (generally referred to as data). Network interface160 may enable wired and/or wireless communications (e.g., NFC orBluetooth) to and/or from information handling system 100.

In particular embodiments, network 110 may include one or more routersfor routing data between client information handling systems 100 andserver information handling systems 100. A device (e.g., a clientinformation handling system 100 or a server information handling system100) on network 110 may be addressed by a corresponding network addressincluding, for example, an Internet protocol (IP) address, an Internetname, a Windows Internet name service (WINS) name, a domain name orother system name. In particular embodiments, network 110 may includeone or more logical groupings of network devices such as, for example,one or more sites (e.g. customer sites) or subnets. As an example, acorporate network may include potentially thousands of offices orbranches, each with its own subnet (or multiple subnets) having manydevices. One or more client information handling systems 100 maycommunicate with one or more server information handling systems 100 viaany suitable connection including, for example, a modem connection, aLAN connection including the Ethernet or a broadband WAN connectionincluding DSL, Cable, T1, T3, Fiber Optics, Wi-Fi, or a mobile networkconnection including GSM, GPRS, 3G, or WiMax.

Network 110 may transmit data using a desired storage and/orcommunication protocol, including, but not limited to, Fibre Channel,Frame Relay, Asynchronous Transfer Mode (ATM), Internet protocol (IP),other packet-based protocol, small computer system interface (SCSI),Internet SCSI (iSCSI), Serial Attached SCSI (SAS) or another transportthat operates with the SCSI protocol, advanced technology attachment(ATA), serial ATA (SATA), advanced technology attachment packetinterface (ATAPI), serial storage architecture (SSA), integrated driveelectronics (IDE), and/or any combination thereof. Network 110 and itsvarious components may be implemented using hardware, software, or anycombination thereof.

The information handling system 100 can further include an interposersubsystem 170. The interposer subsystem 170 can be coupled to the systembus 121, such that the interposer subsystem 170 is in communication withany of the processor subsystem 120, the memory subsystem 130, the I/Osubsystem 140, the local storage resource 150 and/or the networkinterface 160.

Turning now to FIG. 2A, FIG. 2A depicts a computing environment 200. Thecomputing environment 200 can be implemented at a printed circuit board(PCB) (not shown). The environment 200 can include a first centralprocessing unit (CPU) socket 202 and a second CPU socket 204. The firstCPU socket 202 can be coupled to a first CPU 230 and the second CPUsocket 204 can be coupled to a base interposer 232. In some examples,the interposer subsystem 170 of FIG. 1 can include the base interposer232.

The CPU 230 (and/or the first CPU socket 202) can include a powerconnector 206 a, a memory bus connector 208 a, a high speed input/outputsignal (HSIO) connector 210 a, and an inter-socket link (ISL/HSIO)connector 212 a. The signals on connector 212 a are configurable betweeninter-socket link and high-speed input/output.

The base interposer 232 is electrically, mechanically, and commutativelycoupled to the second CPU socket 204. The base interposer 232 replaces anon-boot CPU that would typically be coupled to the second CPU socket204. The base interposer 232 can include pads to facilitate connectionwith socket signal pins of the second CPU socket 204. Further, thesecond CPU socket 204 can include spring-loaded pins such that when thebase interposer 232 is coupled with the second CPU socket 204, anelectrical coupling is established between the second CPU socket 204 andthe base interposer 232. To that end, similar to the CPU 230 and thefirst CPU socket 202, the base interposer 232 (and/or the second CPUsocket 204) can include a power connector 206 b, a memory bus connector208 b, a high speed input/output signal (HSIO) connector 210 b, and aninter-socket link (ISL/HSIO) connector 212 b.

The CPU 230 can be coupled to appropriate systems/modules through therespective connectors. For example, the power connector 206 a can beconnected to a voltage regulator 220 a; the memory bus connector 208 acan be connected to one or more memory slots 222 a; the HSIO connector210 a can be connected to one or more I/O connectors (or devices) 224 a;and the ISL/HSIO 212 a can be connected to the ISL/HSIO 212 b of thebase interposer 232.

In some implementations, one or more devices can be connected to thebase interposer 232 such that the base interposer 232 ultimatelyprovides a connection between the CPU 230 and the devices. In someexamples, the ISL/HSIO connector 212 b of the base interposer 232 isfurther connected to the HSIO connector 210 b of the base interposer 232(e.g., a “hairpin” connection). As a result, the ISL/HSIO connector 212a of the CPU 230 is connected to the HSIO connector 210 b of the baseinterposer 232 through the ISL/HSIO connector 212 b—e.g., the CPU 230 isconnected to the input/output signal traces of the base interposer 232.Further, this provides a connection between the CPU 230 and I/Oconnectors (or devices) 224 b that are connected to the HSIO connector210 b of the base interposer 232. In short, signals are passed throughfrom the CPU 230 to signal traces/connectors of the base interposer 232from the (non-boot) second CPU socket 204. Furthermore, the powerconnector 206 b can be connected to a voltage regulator 220 b, and thememory bus connector 208 b can be connected to one or more memory slots222 b.

Referring to FIG. 2B, in some examples, the base interposer 232 canfurther include a signal integrity boost device (SID) 240. Specifically,if the signal between the ISL/HSIO connector 212 b and the HSIOconnector 210 b is below a threshold, the signal integrity boost device240 can boost (or amplify) such signal. For example, the SID 240 can beconnected to the ISL/HSIO connector 212 b and the HSIO connector 210 bsuch that a signal between the ISL/HSIO connector 212 b and the HSIOconnector 210 b is boosted. The SID 240 can include a retimer, aredriver, a bridge, a buffer, and/or a switch.

Referring to FIG. 3A, in some implementations, the ISL/HSIO connector212 b of the base interposer 232 is further connected to the memory busconnector 208 b of the base interposer 232 (e.g., a “hairpin”connection). As a result, the ISL/HSIO connector 212 a of the CPU 230 isconnected to the memory bus connector 208 b of the base interposer 232through the ISL/HSIO connector 212 b—e.g., the CPU 230 is connected tothe memory signal traces of the base interposer 232. Further, thisprovides a connection between the CPU 230 and one or more memory slots222 b that are connected to the memory bus connector 208 b of the baseinterposer 232. In some examples, the memory slots 222 b are furtherconnected to storage devices 223 b. In short, signals are passed throughfrom the CPU 230 to the memory bus connector 208 b of the baseinterposer 232 from the (non-boot) second CPU socket 204 to the memoryslots 222 b. Furthermore, the power connector 206 b can be connected toa voltage regulator 220 b, and the HSIO connector 210 b can be connectedto the I/O connectors (or devices) 224 b.

Referring to FIG. 3B, if the signal between the ISL/HSIO connector 212 band the memory bus connector 208 b is below a threshold, the signalintegrity boost device 240 can boost (or amplify) such signal. Forexample, the SID 240 can be connected to the ISL/HSIO connector 212 band the memory bus connector 208 b such that a signal between theISL/HSIO connector 212 b and the memory bus connector is boosted.

In some examples, referring to FIG. 4A, the interposer subsystem 170 caninclude an interposer stack 401. The interposer stack 401 can includethe base interposer 232 and a top interposer 402. The top interposer 402can be coupled to the base interposer 232. In short, the top interposer402 connects to the bottom interposer 232 to obtain the signals from thedevices in communication with the bottom interposer 232. The topinterposer 402 is electrically, mechanically, and commutatively coupledto the bottom interposer 232. In some examples, the top interposer 402is a high-density connector. In short, the top interposer 402 utilizesthe lanes that were formerly dedicated to inter-processor links (betweenthe CPU 230 and an additional CPU that would normally be coupled to thesecond CPU socket 204) for communication with other devices, describedfurther herein. In some examples, the top interposer 402 can include aquantity of pins to carry four x16 PCIe busses including sidebandsignals (e.g., 512 pins plus sideband pins).

Similar to the base interposer 232, the top interposer 402 can include apower connector 406, a memory bus connector 408, a high speedinput/output signal (HSIO) connector 410, and an inter-socket link(ISL/HSIO) connector 412. The power connector 406 can be connected tothe power connector 206 b of the bottom interposer 232, the memory busconnector 408 can be connected to the power connector 208 b of thebottom interposer 232, the HSIO connector 410 can be connected to theHSIO connector 210 b of the bottom interposer 232, and the ISL/HSIOconnector 412 can be connected to the ISL/HSIO connector 212 b of thebottom interposer 232.

In some implementations, the base interposer 232 provides a connectionbetween the CPU 230 and the top interposer 402, and the one or moredevices can be connected to the top interposer 402 such that theinterposer stack 401 provides a connection between the CPU 230 and thedevices. In some examples, the ISL/HSIO connector 412 of the topinterposer 402 is further connected to high speed input/output (HSIO)cable connectors 420 (e.g., x8 Slimline SFF-8654). As a result, theISL/HSIO connector 212 b of the base interposer 232 is connected to theHSIO cable connectors 420 through the ISL/HSIO connector 412.Furthermore, this provides a connection between the CPU 230 and the HSIOcable connectors 420 through the ISL/HSIO connector 412 that isconnected to the ISL/HSIO connector 212 b of the bottom interposer 232.In short, the interposer stack 401 provides a direct route to the HSIOcable connectors 420 for the CPU 230, with the HSIO cable connectors 420cabled to devices. Furthermore, the power connector 206 b can beconnected to the voltage regulator 220 b, the memory bus connector 208 bcan be connected to one or more memory slots 222 b, and the HSIOconnector 210 b can be connected to the I/O connectors (or devices) 224b.

Referring to FIG. 4B, in some examples, the top interposer 402 canfurther include a signal integrity boost device (SID) 440. Specifically,if the signal between the ISL/HSIO connector 412 and the HSIO cableconnectors 420 is below a threshold, the signal integrity boost device440 can boost (or amplify) such signal. For example, the SID 440 can beconnected to the ISL/HSIO connector 412 and the HSIO cable connectors420 such that a signal between the ISL/HSIO connector 412 and the HSIOcable connectors 420 is boosted. The SID 440 can include a retimer, aredriver, a bridge, a buffer, and/or a switch.

Referring to FIG. 5, in some implementations, the ISL/HSIO connector 412of the top interposer 402 is further connected to a host busadapter/redundant array of independent disks (HBA/RAID) module 520. As aresult, the ISL/HSIO connector 212 b of the base interposer 232 isconnected to the HBA/RAID module 520 through the ISL/HSIO connector 412.Furthermore, this provides a connection between the CPU 230 and theHBA/RAID module 520 through the ISL/HSIO connector 212 a that isconnected to the ISL/HSIO connector 212 b of the bottom interposer 232.Moreover, the HBA/RAID module 520 can be connected to HSIO cableconnectors (or drive connectors) 521—e.g., storage device connections(SATA/SAS drives). In short, the interposer stack 401 provides a directroute to the HBA/RAID module 520 for the CPU 230, with the HBA/RAIDmodule 520 connected to HSIO cable connectors 521. Furthermore, thepower connector 206 b can be connected to the voltage regulator 220 b,the memory bus connector 208 b can be connected to one or more memoryslots 222 b, and the HSIO connector 210 b can be connected to the I/Oconnectors (or devices) 224 b.

Referring to FIG. 6, in some implementations, the ISL/HSIO connector 412of the top interposer 402 is further connected to a field-programmablegate array (FPGA)/application-specific integrated circuit (ASIC) 620. Asa result, the ISL/HSIO connector 212 b of the base interposer 232 isconnected to the FPGA/ASIC 620 through the ISL/HSIO connector 412.Furthermore, this provides a connection between the CPU 230 and theFPGA/ASIC 620 through the ISL/HSIO connector 212 a that is connected tothe ISL/HSIO connector 212 b of the bottom interposer 232. In someexamples, the HSIO connector 410 and the memory bus connector 408 can beconnected to the FPGA/ASIC 620. In short, the interposer stack 401provides a direct route to the FPGA/ASIC 620 for the CPU 230.Furthermore, the power connector 206 b can be connected to the voltageregulator 220 b, the memory bus connector 208 b can be connected to oneor more memory slots 222 b, and the HSIO connector 210 b can beconnected to the I/O connectors (or devices) 224 b.

Referring to FIG. 7A, in some implementations, the ISL/HSIO connector412 of the top interposer 402 is further connected to HSIO slots 720. Asa result, the ISL/HSIO connector 212 b of the base interposer 232 isconnected to the HSIO slots 720 through the ISL/HSIO connector 412.Furthermore, this provides a connection between the CPU 230 and the HSIOslots 720 through the ISL/HSIO connector 212 a that is connected to theISL/HSIO connector 212 b of the bottom interposer 232. Moreover, theHSIO slots 720 can be connected to peripheral component interconnectexpress (PCIe) devices—e.g., x16 PCIe. In short, the interposer stack401 provides a direct route to the HSIO slots 720 for the CPU 230.Furthermore, the power connector 206 b can be connected to the voltageregulator 220 b, the memory bus connector 208 b can be connected to oneor more memory slots 222 b, and the HSIO connector 210 b can beconnected to the I/O connectors (or devices) 224 b.

Referring to FIG. 7B, in some examples, if the signal between theISL/HSIO connector 412 and the HSIO slots 720 is below a threshold, thesignal integrity boost device 440 can boost (or amplify) such signal.For example, the SID 440 can be connected to the ISL/HSIO connector 412and the HSIO slots 720 such that a signal between the ISL/HSIO connector412 and the HSIO slots 720 is boosted.

Referring to FIG. 8, a computing apparatus 800 is shown. The computingapparatus 800 can include a PCB 801 that includes a first CPU socket(not shown) that is similar to the first CPU socket 202 of FIG. 1, and asecond CPU socket 804 that is similar to the second CPU socket 204 ofFIG. 1. The apparatus 800 further includes a CPU (not shown), similar tothe CPU 230 of FIG. 1, coupled to the first CPU socket 802. Theapparatus 800 further includes an interposer stack that includes a baseinterposer 812 coupled to the second CPU socket 804 and a top interposer814 coupled to the base interposer 812. The base interposer 812 and thetop interposer 814 can be similar to the base interposer 232 of FIG. 2and the top interposer 402 of FIG. 4, respectively.

In some examples, a retention mechanism 830 physically couples the topinterposer 814 to the PCB 801. Specifically, when extra support isneeded for the top interposer 814 (e.g., to provide mechanical couplingbetween the interposer stack 810 and the second CPU socket 804), theretention mechanism 830 can provide such extra support. In someexamples, the retention mechanism 830 can include brackets coupled tothe corners 840 of the top interposer 814 that physically couple the topinterposer 814 to the PCB 801.

Referring to FIG. 9, the top interposer 814 is shown coupled to the PB801. Specifically, the apparatus 800 can include memory sockets 950(e.g., DIMM sockets) that the brackets of the retention mechanism 830physically couple the top interposer 814 to. In other words, thebrackets of the retention mechanism 830 clip into the memory sockets950, e.g., clip into the latching mechanism of the memory sockets 950,such that the corners 840 are retained by the memory sockets 950.

Referring back to FIG. 8, the apparatus 800 further includes heat sinkmounting pins 860 and screw holes 862. To that end, the top interposer814 can further be physically coupled to the pins 860 and the screwholes 862, as shown in FIG. 9. The pins 860 and/or the screw holes 862can facilitate alignment between the top interposer 814 and the baseinterposer 812.

The above disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments which fall within thetrue spirit and scope of the present disclosure. Thus, to the maximumextent allowed by law, the scope of the present disclosure is to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing detailed description.

Herein, “or” is inclusive and not exclusive, unless expressly indicatedotherwise or indicated otherwise by context. Therefore, herein, “A or B”means “A, B, or both,” unless expressly indicated otherwise or indicatedotherwise by context. Moreover, “and” is both joint and several, unlessexpressly indicated otherwise or indicated otherwise by context.Therefore, herein, “A and B” means “A and B, jointly or severally,”unless expressly indicated otherwise or indicated other-wise by context.

The scope of this disclosure encompasses all changes, substitutions,variations, alterations, and modifications to the example embodimentsdescribed or illustrated herein that a person having ordinary skill inthe art would comprehend. The scope of this disclosure is not limited tothe example embodiments described or illustrated herein. Moreover,although this disclosure describes and illustrates respectiveembodiments herein as including particular components, elements,features, functions, operations, or steps, any of these embodiments mayinclude any combination or permutation of any of the components,elements, features, functions, operations, or steps described orillustrated anywhere herein that a person having ordinary skill in theart would comprehend. Furthermore, reference in the appended claims toan apparatus or system or a component of an apparatus or system beingadapted to, arranged to, capable of, configured to, enabled to, operableto, or operative to perform a particular function encompasses thatapparatus, system, component, whether or not it or that particularfunction is activated, turned on, or unlocked, as long as thatapparatus, system, or component is so adapted, arranged, capable,configured, enabled, operable, or operative.

What is claimed is:
 1. A computing apparatus, comprising: a printedcircuit board (PCB) including a first central processing unit (CPU)socket and additional CPU socket(s), the first CPU socket including afirst inter-socket link connector; a CPU coupled to the first CPUsocket; a base interposer coupled to the additional CPU socket(s), thebase interposer including a second inter-socket link and a high-speedinput/output signal connector, the second inter-socket link of the baseinterposer connected to the high-speed input/output signal connector ofthe same base interposer; and one or more devices connected to the baseinterposer, wherein the second inter-socket link of the base interposerprovides a connection to both i) the first inter-socket link connectorof the first CPU socket and ii) the high-speed input/output signalconnector of the base interposer such that the first inter-socket linkconnector of the first CPU socket is additionally connected to thehigh-speed input/output signal connector of the base interposer via thesecond inter-socket link of the baser interposer, wherein the baseinterposer provides a connection between the CPU and the one or moredevices.
 2. The computing apparatus of claim 1, wherein the one or moredevices include input/output devices and the base interposer providesthe connection between the CPU and the input/output devices.
 3. Thecomputing apparatus of claim 2, wherein the connection between the CPUand the input/output devices includes a connection between the CPU andinput/output signal traces of the base interposer.
 4. The computingapparatus of claim 1, wherein the one or more devices include memorymodules or devices using memory module sockets and the base interposerprovides the connection between the CPU and the memory modules orsockets.
 5. The computing apparatus of claim 4, wherein the connectionbetween the CPU and the memory modules includes a connection between theCPU and memory signal traces of the base interposer.
 6. The computingapparatus of claim 1, further comprising: a top interposer coupled tothe base interposer, wherein the base interposer provides a connectionbetween the CPU and the top interposer, and the top interposer providesa connection between the base interposer and the one or more devices. 7.The computing apparatus of claim 6, wherein the one or more devicesinclude input/output cable connectors and the top interposer providesthe connection between the CPU and the input/output cable connectors. 8.The computing apparatus of claim 6, wherein the one or more devicesinclude storage devices, and the top interposer provides the connectionbetween the CPU and the storage devices.
 9. The computing apparatus ofclaim 6, where the one or more devices include a field-programmable gatearray (FPGA) devices, and the top interposer provides the connectionbetween the CPU and the FPGA devices.
 10. The computing apparatus ofclaim 6, wherein the one or more devices includes a peripheral componentinterconnect express (PCIe) devices, and the top interposer provides theconnection between the CPU and the PCIe devices.
 11. The computingapparatus of claim 6, wherein the top interposer further includes asignal integrity boost device.
 12. A computing apparatus, comprising: aprinted circuit board (PCB) including a first central processing unit(CPU) socket additional CPU socket(s), the first CPU socket including afirst inter-socket link connector; a CPU coupled to the first CPUsocket; and an interposer stack including: a base interposer coupled tothe additional CPU socket(s), the base interposer including a secondinter-socket link and a high-speed input/output signal connector, thesecond inter-socket link of the base interposer connected to thehigh-speed input/output signal connector of the same base interposer; atop interposer coupled to the base interposer, wherein a retentionmechanism physically couples the top interposer to the PCB, wherein thesecond inter-socket link of the base interposer provides a connection toboth i) the first inter-socket link connector of the first CPU socketand ii) the high-speed input/output signal connector of the baseinterposer such that the first inter-socket link connector of the firstCPU socket is additionally connected to the high-speed input/outputsignal connector of the base interposer via the second inter-socket linkof the base interposer.
 13. The computing apparatus of claim 12, whereinthe retention mechanism includes a bracket coupled to the topinterposer, the bracket physically coupling the top interposer to thePCB.
 14. The computing apparatus of claim 13, further comprising aplurality of memory sockets, wherein the bracket physically couples thetop interposer to the memory sockets.
 15. The computing apparatus ofclaim 12, further comprising a plurality of heat sink mounting pins,wherein the top interposer is physically coupled to the heat sinkmounting pins.
 16. The computing apparatus of claim 15, wherein the heatsink mounting pins align the top interposer with the base interposer.17. The computing apparatus of claim 12, further comprising one or moredevices connected to the top interposer, wherein the top interposerprovides a connection between the CPU and the one or more devices.